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© Copyright 2009 | Tejaswy Hari

TEJASWY HARI
 
 
My Research
 

I am working as FPGA Design Engineer for WiNC2R - Winlab Network Centric Cognitive Radio.

My work includes

  • Design of physical layer blocks - modulator, demodulator, header extractor and frame checker in VHDL
  • Setup automated test benches for the processing engines mentioned above and Simulation in Modelsim
  • Integrating all sub-blocks into the top-level architecture and Implementing the FPGA
  • Setup DEMO to send frame through the Tx-Rx chain

Knowledge in

  • C, C++, VHDL, Matlab
  • Modelsim, Xilinx Embedded and Software Development Kit, Xilinx ISE, ChipScope, Simulink
  • Virtex 5 FPGA
       
 

MASTERS THESIS

"Physical Layer Design and Analysis of WINLAB Network Centric Cognitive Radio"
October 2009

Click here to download slides

Kindly email me at
tejaswy[at]winlab[dot]rutgers.edu
for Thesis Document