Brief Description of Current Work

Turbo Codes for Frequency Selective Fast Fading Wireless Channels

The Broad Band Mobility (BBM) group in WINLAB is looking at ways to enable reliable high speed communication of broadband data over doubly dispersive wireless channels. I am working on the channel coding aspects. I have implemented a Turbo Encoder and Decoder and tested its performance over AWGN and a perfectly interleaved Rayleigh Fading channel. The decoder uses the BCJR algorithm in the log domain (Log-MAP and Max-Log-MAP), upto 8 iterations. Future scope of work is still open and includes Turbo decoding for higher order modulation schemes and Turbo Equalization.   

Presentations Given:

• At the National Conference of Communications (NCC-2002) held at IIT Bombay, on January 2002, about the paper "A Simulation Testbed for Performance Evaluation of Open Loop Power Control Algorithms for Cellular CDMA". Click here for the presentation. Click here for the paper

•  An  Tutorial on "Theory of Digital Signal Processing". This was the introductory talk of a 3 day Orientation Program "Programming in Motorola's Starcore DSP tool", held at the GS Sanyal School of Telecommunications, IIT Kharagpur,  on summer 2002. Click here for the presentation.

•  A talk at the PHY Meeting, WINLAB about  "The Impulse Radio – Waveform Characteristics and BER Analysis" on October 2002. Click here for the presentation.

•  A talk about "Implementation and Performance Evaluation of an OFDM Modem" as part of the Communication Theory class at Rutgers. Click here for the presentation

Brief Description of Earlier Work

Power Control Issues in Cellular CDMA

 This work was part of the Project  "Physical Layer Design Issues in WCDMA" which was a collaboration between IIT Kharagpur and National Semiconductors Inc. USA.  Power control algorithms are very important for increasing the average traffic and quality of service in CDMA systems. Some interesting open loop power control schemes, namely ‘Power Truncation’ and ‘Power Limitation’ algorithms have been proposed in literature. The work describes a simulation testbed developed for carrying out performance studies on the two algorithms. It also verifies some of the analytical results. Based on the work, a paper was communicated to the National Conference of Communications, (NCC-2002) held at IIT Bombay. Click here for the paper.

VLSI  Implementation of a Digital Baseband Transceiver

This work was part of a Project in designing Software Radios, which was a collaboration between IIT Kharagpur and National Semiconductors Inc. USA. The plan was to design and fabricate a baseband communications processor, which could support data at the E1 rate of 2.048 Mbps. The transmitter was designed to accept bits at 2.048 Mbps, add header and tail bits to form frames at 2.56 Mbps, split the bits into inphase and quadrature paths, differentially encode data, do interpolation  and digitally encode them using a RRC filter. The receiver was designed to accept this data, do decimation, RRC filtering, joint ML symbol timing and carrier phase recovery, training sequence detection, symbol detection and decision and differential decoding. We also had receiver blocks for estimating the mean and variance of the noise process, which corrupted the signal. In addition, the transmitter and receiver had independent timing units, for overall synchronization purposes. We used the 0.25 micron CMOS technology libraries of National Semiconductors, Synopsis and Cadence design tools for front and back end designs respectively. The chip was called KGP-BBPRO (we tried to come up with a more innovative name, but were constrained by time and 5 letters!) and was fabricated at National Semiconductors Fabrication Lab at Atlanta, GA. The chip is currently being tested at KGP. For a description of the chip click here.

If you are interested in VLSI related research at IIT Kharagpur visit  http://www.vlsi.iitkgp.ernet.in  It is simply a great place to grow and learn!