Previous Projects - 1999
Author: Tanja Cuk
Home Institution: Princeton University
Date: 08/06/99
Instructor: Wagner Group
Title: FORMING PRECURSOR COPPER LINES BY EVAPORATIVE COOLING
The purpose of the project was two-fold: investigating the "coffee stain effect" and developing a way to print copper lines for Integrated Circuit design. A precursor copper solution was made by dissolving copper hexanoate in a solvent. It was then printed on clean glass slides using pipettes with inner diameters between 50-100um and outer diameters of 250-500um. The solvent evaporated leaving behind copper hexanoate lines. A surface profiler obtained the profiles of the lines. The results indicated the "coffee stain effect"-the copper hexanoate solute piled up at the edges of the line. The characteristics of these lines varied based on the concentration and volume of solution put down.
Author: Brett Diamond
Home Institution: Carnegie Mellon University
Date: August 4, 1999
Instructor: Dr. James C. Sturm
Title: Profile Analysis of Ink-Jet Printed Polymer Drops
Over the past few years, there has been interest in the use of ink-jet printing for the fabrication of polymer-based organic light emitting diodes (OLEDs) and thin film transistors (TFTs). The patterning of such devices introduces the possibility of low-cost large-area electronics with flexible plastic substrates for display or data storage applications (e.g. flat panel displays). Furthermore, ink-jet printing would reduce the time and cost associated with traditional photolithography used in device fabrication. Before considering ink-jet printing as a patterning technology, we must understand the dynamics behind the evaporation of polymers and fluorescent dyes (used in OLEDs). Much work has already been done to model the formation, spreading, and evaporation
of liquid droplets on a flat surface. Through these studies, the surface tension and wettability of that surface was found to significantly affect the entire process, including the formation and development of a ring structure (usually referred to as the "coffee stain affect.")
My research focused on three different questions: 1) How can we predict the drop profile of a liquid before dispensing onto the substrate? 2) How can we characterize that profile once the liquid has evaporated? 3) How can we pattern substrates to produce uniform polymer films when dropped from an ink-jet printer? To help answer these questions, I learned to operate a piezoelectric-based printing machine that can dispense small drops of polymers at various control parameters (e.g. voltage, frequency, etc). Contrary to most ink-jet printers, this machine helps us learn how to predict the size, volume, and shape of a droplet. Since temperature plays an important role in the evaporation of a liquid and the segregation of polymer molecules, I studied the drop profile after evaporation of PVK, a chloroform-based hole-transport polymer that is used in OLEDs. At colder temperatures, the polymer distributes itself more uniformly, but still contains outer and inner ring structures.
Since the formation of polymer layers in OLEDs and TFTs require accurate positioning, it becomes useful to pattern different regions of a substrate that would account for the fault tolerance of a low cost ink-jet printer. During my research, I investigated the formation of an inkwell that contained a hydrophilic base made of Indium Tin Oxide (ITO) and hydrophobic walls made of photoresist. Photoresist is useful because it can be patterned onto ITO through conventional lithography. However, this process proved unsuccessful because the various solvents used in the process altered the hydrophilic nature of the ITO substrate. Future research might involve other hydrophobic materials patterning techniques such as laser etching.
In conclusion, ink-jet printing polymers for the fabrication of OLEDs and TFTs adds more fuel to the exciting race towards flexible plastic electronics, including large-scale flat panel displays, because it offers a low-cost alternative to the more expensive and complex traditional patterning techniques.
Author: Stefan Adrian Gradinaru
Title: Low Noise, Low Power, Low Temperature Amplifier
As a student in the Princeton University Summer Institute, working in the lab of Prof. Dan Tsui, under the supervision of Dr. Michael Hilke, I was given the task of building a low noise, low power, low temperature amplifier. The main purpose for this amplifier was to be used as a follower stage for low temperature measurements of various high impedance loads. The circuit design was simple, but the restrictions imposed by desired performance, made this project a challenging task. These requirements included:
- low noise (<10 nV);
- low power consumption (<50 uW);
- low operating temperature (30 mK);
- high bandwidth ( > 1 MHz);
- optimum gain at low temperature (1-20 at 30 mK);
- small size;
- low cost.
Due to the high frequency requirement along with the low operating temperature and reduced noise, the best choice for the amplifying transistor in the circuit was a HEMT (high electron mobility transistor). The transistor used was a NEC GaAs HJ-FET L to S band low noise amplifier (NE 34018). The typical characteristics for this transistor given by the company were: at room temperature were: low noise (0.6 dB at 2GHz), high associated gain (16 dB at 2GHz), saturation drain current (IDDS) of 80mA, and leakage current (IGSO) of 0.5 mA. However the characteristics for the HEMT at low temperature were not known. Thus in the first stage of my project I fully characterized this transistor at low temperature (4K). Data was taken using LabView instrumentation software and the graphs were created using Origin 5.0 . Due to the high saturation current I had to build a current source which allowed me to do the required measurements. This was done using a BJT emitter follower circuit. A schematic of the current source/voltage source is shown below:
First I reproduced the claimed characteristics of the HEMT at room temperature. There were two types of sweeps done - VGS sweeps at constant VDS, and VDS sweeps at constant VGS. My results were well within the ranges given for the transistor parameters and actually very close to the typical values (IDDS = 80mA, Ileak = 0.5mA). At low temperature the transistor behavior was similar in the shape of the curves but different numerically. The saturation current at a gate voltage of 0 V was around 20 mA for VDS = 7 V. The conduction channel was closed at VGS = -1 V. The VGS sweeps were also interesting. I noticed that current increased sharply around VGS = -0.5 V and then it saturated for VGS between -0.75 V and 1 V, with values between 3 mA and 25 mA depending on the value of the VDS (0.1-3V). The measured leakage current was very low (<10 nA) which was low enough for the requirements. Using all the data collected I was able to create a graph of the transistor gain vs. power for various gate voltages which was crucial in establishing the optimum operating point of the amplifier. Taking a desired power consumption of 50 mW I was able to determine that for the highest gain the transistor should be operating at a gate voltage around -0.55V. With that information in hand I was ready to start building the actual amplifier.
The basic design of the amplifier is shown in the figure below. It was intended to minimize the number of required components because all resistors and capacitors introduce more noise, and they take up more space. The values of the components are shown.
The resistors were chosen such that for a VDD voltage of 12 V the gate voltage would be optimum VGS = -0.55 and VDS would be such that the power consumption would be bellow 50mW. The capacitors were used to as high pass filters at the input and the output (aiming for a range of 100-300Hz) and a low pass filter at the transistor source (aiming for <1kHz).
Due to the noise concerns a 12 V battery was used to provide the VDD. This battery was enclosed in an insulated box grounded to the common outside ground. A HP signal generator was used for the input with a 40mVpp sine wave. The output signal was analyzed with a HP oscilloscope and a HP signal analyzer.
At room temperature the maximum gain of the amplifier was 20, and at low temperature the highest gain for which the output waveform was undistorted was 10. It was realized immediately that the gain of the amplifier was not a concern. In the next phase, the noise level of the design was measured and analyzed. At first the noise was very high, with peaks in the range of mV at 60Hz and it's multiples and also at 56kHz due to the other instrument running on AC outlet power in the lab. At one point we measured that our dipping probe was picking up an 8 Vpp 60Hz signal which destroyed a few transistors used. Better insulation and grounding helped us rapidly remedy the major problems were and the more delicate refinements of the system were soon explored. We used coaxial cables outside and inside the probe. Only the inside cable of the coax was used to carry the signal, as the outside was grounded for better shielding. Eventually I was able to reduce the noise level down more than 1000 times (520nV at 60 Hz, with non-peak noise levels in the 100-200nV range). The noise was at desired design levels.
The next concern was bandwidth. At a first measurement I obtained a bandwidth of 30 kHz. That was alarming knowing that my goal was in the MHz range. I then looked by at my design and tried to identify the reason for which this values was so small. It was obvious that the transistor was not limiting my amplifier - its bandwidth is in the GHz range. It had to be a low-pass filter. I realized that the coaxial cables that I was using were introducing a parasitic capacitance between the output and the ground (1pF/cm) which, combined with the output impedance of the amplifier (~20kW), were creating a low pass filter cutting off my bandwidth at 30kHz (exactly what I noticed experimentally). The solution was either to reduce the parasitic capacitance or the output impedance of the amplifier. To reduce the output impedance of the amplifier I could have done a couple of things: add another stage - but that would have increased power consumption and it was not desired, I could have reduced the value of the gain considerably - thus that was not an option either. The only thing I could do was to reduce VDD, which would reduce the ID current thus reducing impedance. But that would not be enough. I also had to reduce the parasitic wire capacitance. Our first solution was to separate the ground of the amplifier from the gourd of the measurement instruments (outside ground) and have it floating. That way the output signal carried by the coaxial cable would be in proximity with a different ground than the one causing my cutoff, thus reducing capacitance significantly. I did implement this idea and my bandwidth increased to a maximum of ~100kHz. However there were problems with this design. My input from the signal generator was different as seen by the amplifier because the grounds were different. Also the output seen by the oscilloscope was different then the real amplifier output, again because of the difference in the two grounds. It was obvious that it was not possible to have a floating ground. The solution was to disconnect the shielding part of the coax cables from the ground and from each other. Each was connected to a piece of copper that served as an electron sink stabilizing the electrostatic state of the wires. This way the capacitance between output, VDD, input and ground was reduced significantly.
The final measurement indicated the following:
Room Temperature
VDD Gain Bandwidth
12 V 20 200kHz
7.7 V 1 > 2Mhz
Low Temperature (4K)
VDD Gain Bandwidth
6.5 V 8 750kHz
5.7 V 2 1.5Mhz
5.5 V 1 > 2MHz
The intended goals of the project were met. This amplifier can be used for applications at low temperature requiring very low noise, power, and high bandwidth.
Throughout the research period various obstacles were encountered that were sometimes easy to resolve and sometimes more difficult. But I believe that going through the process of problem solving taught me a lot, and if I had to do it all over again I would probably be able to finish everything in a much shorter period of time. I have learned a lot this summer from my mentors, my books, my work, and especially from my mistakes.
Author: Philip Jones
Home Institution: Southern University
Date: August 5, 1999
Instructor: Professor James C. Sturm/Dr. Duane L. Marcy
Title: Using Computer Aided Research & Development (CARD) for Optimizing a Silicon Plasma Etching Process
The purpose of my research project is to produce microscopic channels for the DNA research conducted by the biophysics group at Princeton University. In order to create these channels, I needed to find a recipe for the plasma etcher that would produce a fast silicon etch rate, a high selectivity, and a greater etched depth than required for transistors. Therefore, we needed to determine what were the variables involved in the plasma etcher, and determine which variables were responsible for producing a high etch rate, and a high selectivity. We found that there were six variables that could be altered in the plasma etcher, which were the power, pressure, chlorine, argon, boron trichloride, and hydrogen. Since it would take too long ot try a hit or miss approach with each variable, we used the Computer Aided Research & Development (CARD) program to design the experiments. Once the experiments were performed, we could then later input the data, and see what effect each different variable had on the etch rate and selectivity.
It was found that an increase in power or chlorine increased the etch rate, low amounts or high amounts of argon increased the etch rate, pressure and boron trichloride had no effect on the etch rate, and an increase in hydrogen actually lowered the etch rate. It was found for the selectivity, that as you increased either the pressure or argon, the selectivity increased. However, the power, chlorine, boron trichloride, and hydrogen had no effect on the selectivity. We therefore concluded that the recipe for the fastest etch rate and highest selectivity would come from using high power (400W), high pressure (100mTorr), high argon (40sccm), high chlorine (40sccm), and no boron trichloride nor hydrogen. When we performed this experiment, we achieved a very fast silicon etch
rate of 5773 angstroms/minute, and a high selectivity of 34.3, thereby showing that the recipe worked.
Author: Christin Lundgren
Home Institution: Bucknell University
Date: August 2, 1999
Instructor: Prof. Keren Bergman, Keir Neuman
Title: Optical Trapping
The purpose of my project was to research possible ways of prolonging cell life
by preventing photodamage from an optical trapping laser. It has been found that
e. coli grown in an anaerobic environment are not subject to this type of
damage, but anaerobic conditions are not practical for viewing cells in vivo. It
was hypothesized from previous research that the damage was being caused by an
oxygen radical. We therefore tried growing and viewing e. coli cells in the
presence of various known antioxidants. We grew cells in DABCO, DMF, histidine,
and beta-carotene. Unfortunately, none of these has been effective in prolonging
cell life. In fact, the data show cell lifespan decreasing by about a factor of
two in the presence of each of these substances.
Author: Charles Peach
Home Institution: Princeton University
Date: August 5, 1999
Instructor: Advisor: Wayne Wolf
Title: Data Streaming Digital Video
The objective is to devise a system that can convert the analog output of a CMOS camera into digital format and then stream this digital data into a DSP for further processing. Several significant issues arise when considering digital video: First, large amounts of data must be transferred to provide adequate information for video. When considering the particular model of camera being used for the project, all transmission lines, operational amplifiers, and analog/digit converters must operate with a bandwidth of over 30 MHz. Also, the component purchased for the project must be packaged in a manner that allows an individual to construct the system with minimal manufacturing resources (e.g. DIP packaging). Disappointingly, surface mount components, industry's most prevalent packaging type, cannot be used. The final major issue was locating a moderately priced processor with large I/O capabilities to manage the digit signal. Analog Device's Sharc processor was elected for this task.
Author: Nicholas Peters
Home Institution: Hillsdale College
Date: August 3, 1999
Instructor: Helena Gleskova and Siguard Wagner
Title: a-Si:H TFT Threshold Voltage Shifts
The purpose of our summer project was to investigate the stability of different low-temperature amorphous silicon thin-film transistors (a-Si:H TFTs) deposited at 150°C. It is known that during the operation of standard a-Si:H TFTs deposited at 250 -350°C, a shift in the threshold voltage occurs due to a breaking of the Si-Si bonds in amorphous silicon and /or charge trapping in the gate dielectric. In high-quality TFTs the former effect dominates. We measured the voltage shifts as a function of the number of complete trials. We defined a trial to include two sweeps of gate voltages from -10V to 20V, the first through the linear operation regime and the second through the saturation regime. Each working transistor was tested for 30 trials recording the first measurement and each fifth successive measurement. We then calculated the field-effect mobilities, the threshold voltages, the on currents, and the off currents. It was found that the TFTs change in threshold voltage was linearly increasing over the trials tested while the other parameters were constant.
Author: Stephen Raif
Home Institution: Angelo State University
Date: Summer 1999
Instructor: Professor Sigurd Wagner/Doctor Helena Gleskova
Title: Effects of Strain in Hydrogenated Amorphous Silicon
The goal of my project was to measure the effects of strain in hydrogenated amorphous silicon(a-Si:H). We decided to do this by monitering the changes in the gap states of a-Si:H by measuring the absorption coefficient across a wide range of low energy wavelengths. Thus, we used CPM (the constant photocurrent method), which has the ability to measure the absorption coefficient in lower energy regions where the deep defects are located.
Our samples for measurement had a substrate layer of kapton, an insulating layer of silicon nitride, and a surface layer of hydrogenated amorphous silicon. We measured the absorption coefficient spectrums of these samples initially, and then we strained the samples around cylinders of known radius. After measuring the spectrum in this stretched position, we released the sample and measured it once again in its relaxed
state. Then, we continued to increase the strain to the samples by using cylinders of smaller radius and to measure the absorption coefficient spectrums before and after the stress. Our results were somewhat inconsistent; however, we did notice a few general trends. When a sample is first strained, the number of deep defects in the sample increases. Then, when the sample is released, the sample goes through a recovery process in which the sample seems to have fewer defects than it had initially. We measured the number of defects of several samples, but these numbers are fairly inconsistent. Also, we had some trouble with the silicon nitride layer affecting the photocurrent. Future experiments of this nature should exclude the insulating SiNx
layer by using a substrate other than kapton.
Author: Casey Richardson
Home Institution: Worcester Polytechnic Institute
Date: 08/06/99
Instructor: Dr. Keren Bergman
Title: Node Power Supply for Electro-Optic Network
This project consisted of two separate parts. The first part involved the early research and design of a power supply for an electro-optic network. My work consisted of a literature review and some initial design. The second part was the implementation of a PI Controller, which is used in reducing error in electrical signals. The controller was tested on a breadboard, soldered, and fit into a box for later use in the lab.
Author: HowZan Tai
Home Institution: Carnegie Mellon University
Date: August 3, 1999
Instructor: Prof. S. Y. Kung / Mr. Toyokazu Hori
Title: Music Score Recognition
The purpose of this project was to create a JAVA application that recognized bitmap images of music score and outputs a midi file. The process involved Principal Component Analysis (PCA) analysis to correct the rotational angle of the image. There was a problem with the segmentation so a new segmentation was created in order to detect notes with longer stems. The densities were used as input
patterns for the hierarchical Decision Based Neural Network (DBNN). Finally a midi file, assembled from the original music score was created and played.
Author: Edward Tang
Home Institution: Johns Hopkins University
Date: August, 1999
Instructor: Professor Bede Liu
Title: Digital Watermarking - Embedding in the Frequency and Spatial Domain
My research in the Electrical Engineering Multimedia Lab at Princeton University was in digital watermarking. I had two main thrusts to my work: the first was in color images, where my goal was to determine the feasibility and specifics of embedding information in the frequency domain of a random, natural image, and the second was in binary (black and white) images, and my focus there was to develop a method for adding extra,
imperceptible information in the spatial (or time) domain of an image.
An important consideration in watermarking schemes is the ability of the embedded information to survive image compression. The scheme that I analyzed was able to do this by selectively altering the embeddable (most significant) coefficients of an image after it had been transformed into the frequency domain and quantized by the compression scheme. To investigate the nature of these embeddable coefficients, I developed a program to compress an image (using the JPEG standard), gather information about the percent of embeddable coefficients as well the distribution of
significant coefficients in an image, and to compare the data within a large-volume image library. The analysis showed that 1) on the average twelve percent of each image had potential for embedding information 2) images with more textures and edges had a significantly larger number of 'significant' coefficients 3) distributions of embeddable coefficients varied depending on combination of smooth and textured areas in an image,
regardless of the percentage of embeddable coefficients in the image itself 4) higher visual quality compression of images (less loss) resulted in more embeddable coefficients than lower visual quality compression (larger quantization steps.)
For binary images, which contain mostly print or scanned text, there is a slightly different approach to watermarking that involves flipping certain bits in the spatial domain (as opposed to the frequency domain) to add the extra information. My objective was to develop a set of rules to determine the best bits to be flipped (that would be the least noticeable to change) by examining the eight-connected neighborhood around each pixel, and to evaluate the scheme to see how 'good' it was. I created a set of rules based on object-separation and 'post-flip' and 'pre-flip' connectivity, and then I implemented this methodology in a 'flipping' program, and evaluated the results. I found that 'flippable' bits could not be flipped too close to one another, without sacrificing visual
quality, and also that flipping bits in a foreground artifact (the dots of i's and j's, for example) was very noticeable to the eye, and needed to be avoided. I rectified both problems by adding to my code, and the end result was a satisfactory one, although the number of bits that could be flipped still had to be determined experimentally because the
concentration of foreground pixels varied from image to image.
I would like to thank Professor Liu for his guidance, Min Wu for her help on the first leg of my research, and everyone who made PSI-EE '99 possible.
Author: Andy Vidan
Home Institution: Cornell University
Date: August 3, 1999
Instructor: Professor Daniel C. Tsui
Title: Double Quantum Wells: Independently Contacting Two-Dimensional Electron Systems
The main goal of my project is to observe the quantum phase transition of gallium arsenide (GaAs) semiconductor material in two dimensions under zero magnetic field. However, being that this is the first stage of this project, my short term goal was to make independent electrical contacts on a GaAs/AlGaAs double quantum well system and to characterize the sample by measuring the resistivity, carrier density, and mobility. The measurements from the sample are intertwined with various aspects of the integral and fractional Hall effect I first built a probe which holds the 16-pin socket on which we place the GaAs sample. This probe allows you to "dip" the sample into a helium tank that is at about 4.2K. Then, I made independent electrical contacts on the sample. The contacts, consisting of front and back gates, allows us to switch between the quantum wells in the semiconductor.
While working on this project I was able to study the physics of
semiconductor,s and I learned how to develop these semiconductors. I learned how to use a mask aligner and an evaporator. Also, I used photolithography extensively in my research. Furthermore, I also had a chance to study low temperature and two-dimensional physics.
Author: Neil Vachharajani
Home Institution: Princeton University
Date: 8/4/1999
Instructor: Professor James C. Sturm
Title: Organic Thin Film Transistors - Fabrication and Characterization
Organic semiconductor devices such as organic thin film transistors (TFTs) have recently received significant interest because of their possible application in flexible displays and integrated circuits. The technology will eventually allow for small to medium scale integration to occur on flexible plastic substrates as opposed to conventional silicon substrates. In order for organic TFTs to become a viable alternative to amorphous hydrogenated silicon TFTs, it is important for them to have comparable mobility and ON/OFF current ratio while remaining economical to produce.
My research focused on inexpensively fabricating organic TFTs and improving their device characteristics. The TFTs fabricated consisted of a heavily doped silicon substrate, a layer of thermally grown silicon dioxide (glass), a thin layer of regioregular poly (3-hexylthiophene), and evaporated gold source/drain contacts. The hexylthiophene is the organic semiconductor layer. The silicon acted only as the gate for the transistor and did not act as a semiconductor. It was used because of the ease of growing a uniform high quality insulator on top of it.
The majority of my research focused on improving the characteristics of the TFTs by trying to influence the molecular ordering of the thiophene layer. It was my understanding that the technique used to deposit the thiophene had a significant effect on the molecular ordering of the layer. The two techniques I tried were spin coating and dip coating.
The results of my experimentation showed that dip coating was a more effective method of depositing the thiophene. However, both dip coated and spin coated samples suffered from low mobility and overwhelming off current. By annealing the transistors under nitrogen, I was able to dramatically lower off currents in the transistors. Unfortunately, I was unable to improve the field-effect mobility of the thiophene. Further research in this area would involve improvement of mobility, usage of plastic substrates and organic insulators, and ink-jet printing techniques for fabrication.
Author: Matt Ziegler
Home Institution: University of Virginia
Date: 8/4/99
Instructor: Prof. Wayne Wolf
Title: VLSI and Architecture for Video Signal Processors
With recent advances in processing power, multimedia technology has become one of the fastest growing areas in computing. Digital video, in particular, has emerged as an indispensable medium for information exchange. However, digital video algorithms are also among the most computationally intensive in the field of signal processing, which presents difficulties for even high-end processors. A video signal processor (VSP), which is architecturally designed for video signal processing, is one of the more effective solutions for efficiently processing digital video. VSP's are designed with a system architecture that takes advantage of the natural characteristics of a video signal, such as massive parallelism, high bandwidth, and low latency. The goal of this project is to develop the system architecture and the full-custom VLSI implementation of a single-chip VSP. Our processor will employ a pipelined VLIW (Very Long Instruction Word) architecture and development is aimed at the 0.25um CMOS technology.
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