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Margaret R. Martonosi

In recent years, power and thermal issues have moved from being niche issues of importance in portable systems, to being first-order design constraints in nearly all types of computer systems. In high-performance systems, thermal and power constraints are significant in shaping design choices and limiting computer performance. My research group has played a leading role in analyzing and improving power-efficient design, particularly in high-performance computer systems.

Recent research highlights include:

• Architecture-Level Power Modeling: The Wattch power-modeling infrastructure developed by our group can be used for architectural level power analysis and optimizations. Wattch was an early demonstration that early-stage power analysis (before completion of the chip's circuit designs and floorplans) can be performed both accurately enough and quickly enough to help guide computer architects towards power-aware design choices. The Wattch models have been available for download from our website for slightly over a year now, and are in wide use. Wattch power models have also been ported by other research groups into other simulator frameworks.
• Decay-based Leakage Control: Leakage, or sub-threshold, current is of growing concern to computer architects. In CMOS design, dynamic (or switching) power has been the main focus for many years, because it represents more than 90% of the power dissipation in most chips. But as technologies move forward, leakage power's contribution to total power is growing exponentially; some have predicted that static and dynamic power will be evenly split within three chip generations. With this in mind, our research group has developed architecture-level methods for managing leakage power. In particular, our work on "Cache Decay" proposes methods for deducing when cache lines store "dead" data, and turning off power to those cache lines to control leakage. This work makes three main contributions. First, it demonstrates a method for reducing cache leakage by 3-4X with essentially no performance impact on average. Because our leakage reduction method draws from the theoretical field of competitive on-line algorithms, we have shown that its power and performance impact can always be theoretically bounded within a constant factor of worst-case. Finally, our timer-based deductions of "dead" data have driven more recent research on a range of power and performance optimizations.
• ZebraNet: In 2001, we began work on a new project called ZebraNet. The ZebraNet project applies our expertise in adaptive, power-aware systems to mobile computing, and in particular to the domain of wildlife tracking. Working with colleagues in Biology and wireless systems, we are building power-adaptive GPS and wireless compute nodes that use ad hoc, peer-to-peer, wireless networking to provide reliable data storage and to propagate tracked data back to researcher base stations. Research issues arise in meeting stringent power limits and reliability requirements in rugged terrain. As with our other research, stochastic analysis and bounding techniques provide a theoretical underpinning for our applied systems-building efforts. Long-term, we plan to deploy second-generation ZebraNet nodes at Princeton's Mpala Research Centre in Kenya.